1. Field of the Invention
The present invention relates to a timing recovery controller and operations method thereof, and more particularly to a timing recovery controller and operations method thereof capable of performing timing recovery at twice a symbol rate.
2. Description of the Prior Art
In digital communication, a transmitter sends a signal sequence carrying symbol data at a specific transmission rate. When a receiver receives the data sequence, the receiver samples the signal sequence with a sampling rate to generate a sampling sequence, so as to recover the symbol data according to a timing base. For example, if the sampling rate is 90 MB and the timing base is 2, a data sequence with a data rate of 45 MB can be acquired. The data sequence includes symbol data and transition data, and the data rate of the data sequence is twice a symbol rate of the symbol data.
However, if there is a timing error between the transmitter and the receiver, resulting from an operating frequency offset of an analog to digital converter (ADC), or a phase delay between the transmitter and the receiver, etc., the sampling rate will be inaccurate, such that the receiver cannot accurately recover the symbol data. In such a situation, the receiver needs to perform timing recovery to acquire the correct symbol data by adjusting the timing base.
In general, the receiver utilizes a timing recovery controller to perform timing recovery. The timing recovery controller includes a timing error detector and a timing lock detector. The timing error detector calculates a timing error to adjust the timing base of the receiver, so as to acquire the correct symbol data. The timing lock detector determines whether timing is locked, so as to adjust operations of the timing recovery controller; for example, the timing error detector stops operations of or reduces operating frequency, etc.
Please refer to FIG. 1, which is a schematic diagram of a conventional timing recovery controller 10. The timing recovery controller 10 includes a clock generator 102, a sampler 104, a timing base device 106, a timing error detector 108 and a timing lock detector 110. The clock generator 102 generates a sampling rate Rs, such that sampler 104 samples a signal sequence Sig_seq according to the sampling rate Rs, so as to generate a sampling sequence Sam_seq. The timing base device 106 acquires a data sequence Data_seq from the sampling sequence Sam_seq at a data rate Rd according to a timing base TB. The data sequence Data_seq includes symbol data Sym_1˜Sym_n and transition data Trans_1˜Trans_n, and a data rate Rd of the data sequence Data_seq is twice a symbol rate Rsb of the symbol data Sym_1˜Sym_n. The timing error detector 108 receives and delays the data sequence Data_seq, and generates a timing error value TE when data of the data sequence Data_seq is any symbol data Sym_x, to adjust the timing base TB. The timing lock detector 110 receives and delays the data sequence Data_seq, and generates a timing lock determination result TL when data of the data sequence Data_seq is any symbol data Sym_y, so as to utilize a control signal Con to stop operations or reduce operating frequency of the timing error detector 108 when the timing lock determination result TL indicates timing is locked. As a result, when data of the data sequence Data_seq is symbol data, the timing recovery controller 10 can adjust the timing base TB or control operations of the timing error detector 108 according to a timing status, to perform timing recovery.
Please refer to FIG. 2A, which is an eye plot for calculating the timing error value TE of symbol data in the prior art. In FIG. 2A, symbol data Sym_a, Sym_(a-1) and transition data Trans_a in the middle are data of the data sequence Data_seq when there is timing error, while symbol data Sym_a′, Sym_(a-1)′ and transition data Trans_a′ in the middle are data of the data sequence Data_seq when there is no timing error. In such a situation, the timing error value TE=(Sym_a-Sym_(a-1))×Trans_a. The timing error value TE greater than 0 indicates the timing is leading, as shown in FIG. 2A, while the timing error value TE less than 0 indicates timing is lagging (not shown).
The structure in FIG. 2B can be derived from the above concept. FIG. 2B is a schematic diagram of the timing error detector 108 in FIG. 1. The timing error detector 108 includes delay units 202, 204, a subtractor 206, a multiplier 208 and a multiplexer 210. The subtractor 206, the multiplier 208 and the multiplexer 210 can be seen as a timing error calculating module 212, for generating the timing error value TE when data of the data sequence Data_seq is symbol data. The delay unit 202 receives and delays the data sequence Data_seq with a data cycle Td corresponding to the data rate Rd, to output a delay data sequence Delay_seq1. The delay unit 204 receives and delays the delay data sequence Delay_seq1 with the data cycle Td, to output a delay data sequence Delay_seq2. The subtractor 206 subtracts data of the delay data sequence Delay_seq2 with data of the data sequence Data_seq, to generate a subtracting result Sub1. The multiplier 208 multiplies the subtracting result Sub1 with data of the delay data sequence Delay_seq1, to generate a multiplying result Pro. The multiplexer 210 outputs the multiplying result Pro as the timing error value TE when data of the data sequence Data_seq is symbol data, to adjust the timing base TB. In other words, when data of the data sequence Data_seq is the symbol data Sym_a, data of the delay data sequence Delay_seq1 is the transition data Trans_a and data of the delay data sequence Delay_seq2 is symbol data Sym_(a-1), and thus the timing error value TE=(Sym_a-Sym_(a-1))×Trans_a.
Please refer to FIG. 3A, which is a schematic diagram of calculating the timing lock determination result TL of symbol data in the prior art. In FIG. 3A, arrows Data_E indicate energy of data of the data sequence Data_seq, arrows Delay_E indicate energy of data of a delay data sequence Delay_seq3 lagging the data sequence Data_seq the data cycle Td, and arrows TL_E indicate energy of data of the data sequence Data_seq minus energy of data of the delay data sequence Delay_seq3 when data of the data sequence Data_seq is symbol data. Long arrows indicate energy of symbol data, middle arrows indicate energy of symbol data minus energy of transition data, short arrows indicate energy of transition data, and the arrows TL_E can be seen as the timing lock determination result TL corresponding to each symbol data of the data sequence Data_seq. As shown in FIG. 2A and FIG. 3A, when there is timing error, energy of transition data is not 0, and thus energy of symbol data minus energy of transition data is not equal to energy of symbol data, which indicates timing is not locked (i.e. there is timing error).
The structure in FIG. 3B can be derived from the above concept. FIG. 3B is a schematic diagram of the timing lock detector 110 in FIG. 1. The timing lock detector 110 includes a delay unit 302, a subtractor 304 and a multiplexer 306. The subtractor 304 and the multiplexer 306 can be seen as a timing lock determination module 308 for generating the timing lock determination result TL when data of the data sequence Data_seq is symbol data. The delay unit 302 receives and delays the data sequence Data_seq with the data cycle Td, to output the delay data sequence Delay_seq3. The subtractor 304 subtracts energy of data of the data sequence Data_seq with energy of data of the delay data sequence Delay_seq3, to generate a subtracting result Sub2. The multiplexer 306 outputs the subtracting result Sub2 as the timing lock determination result TL when data of the data sequence Data_seq is symbol data. The timing lock detector 110 utilizes the control signal Con to stop operations or reduce operating frequency of the timing error detector 108 when the timing lock determination result TL indicates timing is locked, i.e. the timing lock determination result TL is energy of symbol data.
However, in the prior art, the timing recovery controller 10 can only perform timing recovery when data of the data sequence Data_seq is symbol data. In other words, in the prior art, an operating rate is merely the symbol rate, which requires more time to recover timing. Thus, there is a need for improvement.